1. Field of the Invention
The present invention generally relates to video signal processing systems, and more particularly, to systems for eliminating undesired picture artifacts created by digital video signal processing.
2. Background Information
In digital video signal processing systems, it may be desirable to operate in various pixel domains. For example, it is often advantageous to operate in an orthogonal pixel domain where signal samples represent points on a rectangular grid. Performing on-screen display processing in the orthogonal pixel domain eliminates the need for complex skew-correction schemes to prevent jagged edges and jitter on video overlays. For certain applications such as picture-in-picture (“PIP”) processing, using the orthogonal pixel domain not only eliminates such skew-correction schemes (e.g., for insert picture compression and overlay functions), but also simplifies operations such as vertical filtering. In particular, vertical filtering is often performed using a frame combing process where pixels from one field are compared with pixels from a previous field (or frame). Such a process would be extremely difficult, if not impossible, to perform outside of the orthogonal pixel domain.
In some cases, it may be desirable to convert from one domain to another. As an example, it may be desirable to convert a signal to the orthogonal pixel domain (e.g., line-locked, burst-locked) for processing, and then convert it back to the original non-orthogonal pixel domain. The different pixel domains may also be viewed as different clock domains wherein the operation in each domain is controlled by a respective clock signal at a particular frequency and exhibiting a particular timing. In the described example, the orthogonal pixel domain is an example of a first clock domain and the non-orthogonal pixel domain is an example of a second clock domain. Various clock domains are possible and may be selected in accordance with the clock domain that is convenient for the particular form of digital signal processing that is needed. An aspect of using different clock or pixel domains is that conversion between the clock domains may be necessary. For example, to convert data from the non-orthogonal pixel domain to the orthogonal pixel domain requires a variable sample rate converter (“SRC”). A variable SRC employs a conversion ratio that is continuously adjusted in order to maintain (i) a constant number of output samples per horizontal line, and (ii) a predetermined phase relationship between the output samples and horizontal synchronization signals (even as the number of input samples per line varies). Similarly, to convert data from the orthogonal pixel domain back to the non-orthogonal pixel domain requires a second variable SRC referred to herein as a variable inverse-SRC.
In certain systems, both the first SRC and second SRC, or inverse-SRC, require a phase lock loop (“PLL”) in order to control the conversion ratio. In particular, the PLL controlling the SRC adjusts the conversion ratio to produce a fixed number of output samples (e.g., 858) per horizontal line. The PLL controlling the inverse-SRC adjusts the conversion ratio to produce an output sample rate that matches the sample rate at the input of the SRC. In such cases, the system transient response time is the sum of the response times of the two PLLs. Accordingly, the use of multiple PLLs often results in an extended recovery interval for horizontal transients, such as those produced by a head switching operation in a video cassette recorder (“VCR”). Moreover, using multiple PLLs requires additional circuitry, and can also introduce noise into the system. Such noise can thereby cause undesired picture artifacts to be displayed.
Accordingly, there is a need for a digital video system which avoids the aforementioned problems, and thus prevents degradation of system transient response time and noise immunity while also reducing circuitry requirements. The present invention addresses these and other issues.